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authorwdenk <wdenk>2003-09-02 22:48:03 +0000
committerwdenk <wdenk>2003-09-02 22:48:03 +0000
commit12f34241cb9679c27a1ab3561766562f5a515eff (patch)
treee6408a1701c7dabf3e2ceb1326ce2f5cc8657c96 /cpu/ppc4xx/miiphy.c
parent326428cc8bbdddb30920a96b672abd0d59833ce4 (diff)
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* Add support for PPChameleon Eval Board
* Add support for P3G4 board * Fix problem with MGT5100 FEC driver: add "early" MAC address initialization
Diffstat (limited to 'cpu/ppc4xx/miiphy.c')
-rw-r--r--cpu/ppc4xx/miiphy.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c
index 0606ebe..e719a33 100644
--- a/cpu/ppc4xx/miiphy.c
+++ b/cpu/ppc4xx/miiphy.c
@@ -101,6 +101,7 @@ int miiphy_read (unsigned char addr, unsigned char reg,
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
+ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
sta_reg = sta_reg | (addr << 5); /* Phy address */
out32 (EMAC_STACR, sta_reg);
@@ -156,6 +157,7 @@ int miiphy_write (unsigned char addr, unsigned char reg,
sta_reg = reg; /* reg address */
/* set clock (50Mhz) and read flags */
sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
+ sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */
sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
memcpy (&sta_reg, &value, 2); /* put in data */