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| author | Victor Gallardo <vgallardo@amcc.com> | 2008-09-04 23:49:36 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-09-05 12:21:16 +0200 |
| commit | 78d78236896d62bb8ca7302af38d8f1493eb2651 (patch) | |
| tree | 9300399861e3c21aa84b82c03c478b528565489c /cpu/ppc4xx/miiphy.c | |
| parent | f6b6c45840f9b4671d2d97243a12a1f3ffb64765 (diff) | |
| download | u-boot-imx-78d78236896d62bb8ca7302af38d8f1493eb2651.zip u-boot-imx-78d78236896d62bb8ca7302af38d8f1493eb2651.tar.gz u-boot-imx-78d78236896d62bb8ca7302af38d8f1493eb2651.tar.bz2 | |
ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY
This patch adds GPCS, SGMII and M88E1112 PHY support
for the AMCC PPC460GT/EX processors.
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/miiphy.c')
| -rw-r--r-- | cpu/ppc4xx/miiphy.c | 41 |
1 files changed, 38 insertions, 3 deletions
diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index c882720..d303598 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -180,8 +180,10 @@ int phy_setup_aneg (char *devname, unsigned char addr) * * sr: Currently on 460EX only EMAC0 works with MDIO, so we always * return EMAC0 offset here + * vg: For 460EX/460GT if internal GPCS PHY address is specified + * return appropriate EMAC offset */ -unsigned int miiphy_getemac_offset (void) +unsigned int miiphy_getemac_offset(u8 addr) { #if (defined(CONFIG_440) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ @@ -233,6 +235,39 @@ unsigned int miiphy_getemac_offset (void) return 0x100; #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 mode_reg; + u32 eoffset = 0; + + switch (addr) { +#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR) + case CONFIG_GPCS_PHY1_ADDR: + mode_reg = in_be32((void *)EMAC_M1 + 0x100); + if (addr == EMAC_M1_IPPA_GET(mode_reg)) + eoffset = 0x100; + break; +#endif +#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR) + case CONFIG_GPCS_PHY2_ADDR: + mode_reg = in_be32((void *)EMAC_M1 + 0x300); + if (addr == EMAC_M1_IPPA_GET(mode_reg)) + eoffset = 0x300; + break; +#endif +#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR) + case CONFIG_GPCS_PHY3_ADDR: + mode_reg = in_be32((void *)EMAC_M1 + 0x400); + if (addr == EMAC_M1_IPPA_GET(mode_reg)) + eoffset = 0x400; + break; +#endif + default: + eoffset = 0; + break; + } + return eoffset; +#endif + return 0; #endif } @@ -262,7 +297,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) u32 emac_reg; u32 sta_reg; - emac_reg = miiphy_getemac_offset(); + emac_reg = miiphy_getemac_offset(addr); /* wait for completion */ if (emac_miiphy_wait(emac_reg) != 0) @@ -311,7 +346,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned long sta_reg; unsigned long emac_reg; - emac_reg = miiphy_getemac_offset (); + emac_reg = miiphy_getemac_offset(addr); if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) return -1; |