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| author | Stefan Roese <sr@denx.de> | 2009-10-16 10:01:09 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-23 15:56:32 +0200 |
| commit | 92b8964bed0d1b779d9e26be4e16755b5c635415 (patch) | |
| tree | 8dd6de3afc8a93d9103f0c9026c4edd6609f6d53 /cpu/ppc4xx/fdt.c | |
| parent | 30d45c0d3ea2231f9131276ea113595959a0720e (diff) | |
| download | u-boot-imx-92b8964bed0d1b779d9e26be4e16755b5c635415.zip u-boot-imx-92b8964bed0d1b779d9e26be4e16755b5c635415.tar.gz u-boot-imx-92b8964bed0d1b779d9e26be4e16755b5c635415.tar.bz2 | |
ppc4xx: Update flash size in reg property of the NOR flash node
Till now only the ranges in the ebc node are updated with the values
currently configured in the PPC4xx EBC controller. With this patch now
the NOR flash size is updated in the device tree blob as well. This is
done by scanning the compatible nodes "cfi-flash" and "jedec-flash"
for the correct chip select number.
This size fixup is enabled for all AMCC eval board right now. Other
4xx boards may want to enable it as well, if this problem with multiple
NOR FLASH sizes exists.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/ppc4xx/fdt.c')
| -rw-r--r-- | cpu/ppc4xx/fdt.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index b310832..15a184b 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -59,11 +59,17 @@ void __ft_board_setup(void *blob, bd_t *bd) *p++ = 0; *p++ = bxcr & EBC_BXCR_BAS_MASK; *p++ = EBC_BXCR_BANK_SIZE(bxcr); + +#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE + /* Try to update reg property in nor flash node too */ + fdt_fixup_nor_flash_size(blob, i, + EBC_BXCR_BANK_SIZE(bxcr)); +#endif } } /* Some 405 PPC's have EBC as direct PLB child in the dts */ - if (fdt_path_offset(blob, "/plb/opb/ebc") < 0) + if (fdt_path_offset(blob, ebc_path) < 0) strcpy(ebc_path, "/plb/ebc"); rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges, (p - ranges) * sizeof(u32), 1); |