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| author | Larry Johnson <lrj@acm.org> | 2008-01-22 08:51:59 -0500 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-02-14 07:42:32 +0100 |
| commit | 29e3500cbc43c89eff6e720ca83e375deeecd9b3 (patch) | |
| tree | 550d8c4167824d4f9336b52f8b9fb4a539ec769f /cpu/ppc4xx/denali_spd_ddr2.c | |
| parent | ff02f139804f3cb61414f7bbcbfdaa0279e3efae (diff) | |
| download | u-boot-imx-29e3500cbc43c89eff6e720ca83e375deeecd9b3.zip u-boot-imx-29e3500cbc43c89eff6e720ca83e375deeecd9b3.tar.gz u-boot-imx-29e3500cbc43c89eff6e720ca83e375deeecd9b3.tar.bz2 | |
ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code
Signed-off-by: Larry Johnson <lrj@acm.org>
Diffstat (limited to 'cpu/ppc4xx/denali_spd_ddr2.c')
| -rw-r--r-- | cpu/ppc4xx/denali_spd_ddr2.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 825bc21..60f89c9 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -3,7 +3,7 @@ * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core * DDR2 controller, specifically the 440EPx/GRx. * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org. * * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... @@ -77,10 +77,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#if defined(CFG_ENABLE_SDRAM_CACHE) +#if defined(CONFIG_4xx_DCACHE) #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ |