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| author | Haiying Wang <Haiying.Wang@freescale.com> | 2008-10-03 12:37:41 -0400 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:05 +0200 |
| commit | 4ca06607d60d0a6378812ef58fd1eab2a7f77111 (patch) | |
| tree | e145c64ad608f727c0d0f2cbcb54cbeca1c507eb /cpu/ppc4xx/dcr.S | |
| parent | 1f293b417ac6ab8e317ca2b770377ca93edf2370 (diff) | |
| download | u-boot-imx-4ca06607d60d0a6378812ef58fd1eab2a7f77111.zip u-boot-imx-4ca06607d60d0a6378812ef58fd1eab2a7f77111.tar.gz u-boot-imx-4ca06607d60d0a6378812ef58fd1eab2a7f77111.tar.bz2 | |
Add ddr interleaving suppport for MPC8572DS board
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.
* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Diffstat (limited to 'cpu/ppc4xx/dcr.S')
0 files changed, 0 insertions, 0 deletions