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authorStefan Roese <sr@denx.de>2007-01-05 10:38:05 +0100
committerStefan Roese <sr@denx.de>2007-01-05 10:38:05 +0100
commit023889838282b6237b401664f22dd22dfba2c066 (patch)
treea57a564f35070ba04ed56dea78367a2f5d7c13d9 /cpu/ppc4xx/cpu_init.c
parent92eb729bad876725aeea908d2addba0800620840 (diff)
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[PATCH] Add DDR2 optimization code for Sequoia (440EPx) board
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/cpu_init.c')
-rw-r--r--cpu/ppc4xx/cpu_init.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 4b746b0..db0559b 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -31,9 +31,6 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
-
-#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
-
#ifdef CFG_INIT_DCACHE_CS
# if (CFG_INIT_DCACHE_CS == 0)
# define PBxAP pb0ap