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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-10-16 15:01:15 +0200
committerWolfgang Denk <wd@denx.de>2008-10-18 21:54:03 +0200
commit6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch)
treeae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /cpu/ppc4xx/4xx_enet.c
parent71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff)
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rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/ppc4xx/4xx_enet.c')
-rw-r--r--cpu/ppc4xx/4xx_enet.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 6d4d043..d7b16da 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -225,7 +225,7 @@
* Some boards do not have a PHY for each ethernet port. These ports
* are known as Fixed PHY (or PHY-less) ports. For such ports, set
* the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
- * then define CFG_FIXED_PHY_PORTS to define what the speed and
+ * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
* duplex should be for these ports in the board configuration
* file.
*
@@ -237,20 +237,20 @@
* #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
* #define CONFIG_PHY3_ADDR 3
*
- * #define CFG_FIXED_PHY_PORT(devnum,speed,duplex) \
+ * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
* {devnum, speed, duplex},
*
- * #define CFG_FIXED_PHY_PORTS \
- * CFG_FIXED_PHY_PORT(0,1000,FULL) \
- * CFG_FIXED_PHY_PORT(2,100,HALF)
+ * #define CONFIG_SYS_FIXED_PHY_PORTS \
+ * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
+ * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
*/
#ifndef CONFIG_FIXED_PHY
#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
#endif
-#ifndef CFG_FIXED_PHY_PORTS
-#define CFG_FIXED_PHY_PORTS /* default is an empty array */
+#ifndef CONFIG_SYS_FIXED_PHY_PORTS
+#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
#endif
struct fixed_phy_port {
@@ -260,7 +260,7 @@ struct fixed_phy_port {
};
static const struct fixed_phy_port fixed_phy_port[] = {
- CFG_FIXED_PHY_PORTS /* defined in board configuration file */
+ CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
};
/*-----------------------------------------------------------------------------+
@@ -1337,8 +1337,8 @@ get_speed:
#ifdef CONFIG_4xx_DCACHE
flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
if (!last_used_ea)
-#if defined(CFG_MEM_TOP_HIDE)
- bd_uncached = bis->bi_memsize + CFG_MEM_TOP_HIDE;
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
#else
bd_uncached = bis->bi_memsize;
#endif