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| author | Stefan Roese <sr@denx.de> | 2007-06-14 11:14:32 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-06-14 11:14:32 +0200 |
| commit | dbca208518e5e7f01a6420588d1cd6e60db74c2b (patch) | |
| tree | 72d0e07a57fbb9a11935da512803d852063f382b /cpu/ppc4xx/44x_spd_ddr2.c | |
| parent | fba3fb0449b8a54542aed1e729de76e7f5a2ff1b (diff) | |
| download | u-boot-imx-dbca208518e5e7f01a6420588d1cd6e60db74c2b.zip u-boot-imx-dbca208518e5e7f01a6420588d1cd6e60db74c2b.tar.gz u-boot-imx-dbca208518e5e7f01a6420588d1cd6e60db74c2b.tar.bz2 | |
[ppc4xx] Extend program_tlb() with virtual & physical addresses
Now program_tlb() allows to program a TLB (or multiple) with
different virtual and physical addresses. With this change, now one
physical region (e.g. SDRAM) can be mapped 2 times, once with caches
diabled and once with caches enabled.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/44x_spd_ddr2.c')
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 48b9ee2..874cec0 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -144,7 +144,7 @@ typedef enum ddr_cas_id { * Prototypes *-----------------------------------------------------------------------------*/ static unsigned long sdram_memsize(void); -void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value); +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); static void get_spd_info(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -528,7 +528,7 @@ long int initdram(int board_type) dram_size = sdram_memsize(); /* and program tlb entries for this size (dynamic) */ - program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE); + program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); /*------------------------------------------------------------------ * DQS calibration. |