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| author | Stefan Roese <sr@denx.de> | 2007-06-22 10:28:26 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-06-22 10:28:26 +0200 |
| commit | e08e6453fced498b28950f36088c87c0b639a682 (patch) | |
| tree | 5730c11e7440a6b88094d050172b8e5b4b707fbd /cpu/ppc4xx/44x_spd_ddr2.c | |
| parent | d7d5204ce2e0985ff2dfdf3a6b5b6a526cdb1c1e (diff) | |
| parent | 83b4cfa3d629dff0264366263c5e94d9a50ad80b (diff) | |
| download | u-boot-imx-e08e6453fced498b28950f36088c87c0b639a682.zip u-boot-imx-e08e6453fced498b28950f36088c87c0b639a682.tar.gz u-boot-imx-e08e6453fced498b28950f36088c87c0b639a682.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'cpu/ppc4xx/44x_spd_ddr2.c')
| -rw-r--r-- | cpu/ppc4xx/44x_spd_ddr2.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 2ecd3e4..874cec0 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -144,7 +144,7 @@ typedef enum ddr_cas_id { * Prototypes *-----------------------------------------------------------------------------*/ static unsigned long sdram_memsize(void); -void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value); +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); static void get_spd_info(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -465,7 +465,11 @@ long int initdram(int board_type) * Set the SDRAM Clock Timing Register *-----------------------------------------------------------------*/ mfsdram(SDRAM_CLKTR, val); +#ifdef CFG_44x_DDR2_CKTR_180 + mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV); +#else mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG); +#endif /*------------------------------------------------------------------ * Program the BxCF registers. @@ -524,7 +528,7 @@ long int initdram(int board_type) dram_size = sdram_memsize(); /* and program tlb entries for this size (dynamic) */ - program_tlb(0, dram_size, MY_TLB_WORD2_I_ENABLE); + program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE); /*------------------------------------------------------------------ * DQS calibration. @@ -1117,7 +1121,8 @@ static void program_codt(unsigned long *dimm_populated, modt3 = 0x00000000; } if (total_rank == 4) { - codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3); + codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | + CALC_ODT_R(2) | CALC_ODT_R(3); modt0 = CALC_ODT_RW(2); modt1 = 0x00000000; modt2 = CALC_ODT_RW(0); |