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authorProdyut Hazarika <phazarika@amcc.com>2008-08-20 09:38:51 -0700
committerStefan Roese <sr@denx.de>2008-08-21 10:31:16 +0200
commit079589bcfb24ba11068460276a3cc9549ab5346f (patch)
tree85b33c32aaafdedac703834bd763bbf25695f456 /cpu/ppc4xx/44x_spd_ddr2.c
parentba37aa03287c5483c61c0a3e320c8888bee0143a (diff)
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ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ppc4xx/44x_spd_ddr2.c')
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c27
1 files changed, 23 insertions, 4 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 1c36324..c7ed161 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -2172,6 +2172,11 @@ static void program_memory_queue(unsigned long *dimm_populated,
unsigned long i;
unsigned long bank_0_populated = 0;
phys_size_t total_size = 0;
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
+ unsigned long val;
+#endif
/*------------------------------------------------------------------
* Reset the rank_base_address.
@@ -2249,17 +2254,31 @@ static void program_memory_queue(unsigned long *dimm_populated,
}
}
-#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
+ defined(CONFIG_460SX)
+
/*
- * Enable high bandwidth access on 460EX/GT.
- * This should/could probably be done on other
- * PPC's too, like 440SPe.
+ * Enable high bandwidth access
* This is currently not used, but with this setup
* it is possible to use it later on in e.g. the Linux
* EMAC driver for performance gain.
*/
mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
+
+ /*
+ * Set optimal value for Memory Queue HB/LL Configuration registers
+ */
+
+ val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
+ mtdcr(SDRAM_CONF1HB, val);
+
+ val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+ mtdcr(SDRAM_CONF1LL, val);
+
+ val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
+ mtdcr(SDRAM_CONFPATHB, val);
#endif
}