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| author | Grzegorz Bernacki <gjb@semihalf.com> | 2007-09-07 17:46:18 +0200 |
|---|---|---|
| committer | Rafal Jaworowski <raj@semihalf.com> | 2007-09-07 17:46:18 +0200 |
| commit | 15ee4734e4e08003d73d9ead3ca80e2a0672e427 (patch) | |
| tree | 3f175cf322df88a775a2ce86cce0dfe8486abfc1 /cpu/ppc4xx/440spe_pcie.h | |
| parent | a89cbbd27a60e6740772000fd0688ffba1c2576a (diff) | |
| download | u-boot-imx-15ee4734e4e08003d73d9ead3ca80e2a0672e427.zip u-boot-imx-15ee4734e4e08003d73d9ead3ca80e2a0672e427.tar.gz u-boot-imx-15ee4734e4e08003d73d9ead3ca80e2a0672e427.tar.bz2 | |
[PPC440SPe] Convert machine check exceptions handling
Convert using fixup mechanism to suppressing MCK for the duration of config
read/write transaction: while fixups work fine with the case of a precise
exception, we identified a major drawback with this approach when there's
an imprecise case. In this scenario there is the following race condition:
the fixup is (by design) set to catch the instruction following the one
actually causing the exception; if an interrupt (e.g. decrementer) happens
between those two instructions, the ISR code is executed before the fixup
handler the machine check is no longer protected by the fixup handler as it
appears as within the ISR code. In consequence the fixup approach is being
phased out and replaced with explicit suppressing of MCK during a PCIe
config read/write cycle.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Diffstat (limited to 'cpu/ppc4xx/440spe_pcie.h')
| -rw-r--r-- | cpu/ppc4xx/440spe_pcie.h | 16 |
1 files changed, 2 insertions, 14 deletions
diff --git a/cpu/ppc4xx/440spe_pcie.h b/cpu/ppc4xx/440spe_pcie.h index eb7cecf..38745eb 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/cpu/ppc4xx/440spe_pcie.h @@ -38,6 +38,7 @@ #define DCRN_PEGPL_REGBAL(base) (base + 0x13) #define DCRN_PEGPL_REGMSK(base) (base + 0x14) #define DCRN_PEGPL_SPECIAL(base) (base + 0x15) +#define DCRN_PEGPL_CFG(base) (base + 0x16) /* * System DCRs (SDRs) @@ -161,20 +162,7 @@ mtdcr(DCRN_SDR0_CFGADDR, offset); \ mtdcr(DCRN_SDR0_CFGDATA,data);}) -#define PCIE_IN(opcode, ret, addr) \ - __asm__ __volatile__( \ - "sync\n" \ - #opcode " %0,0,%1\n" \ - "1: twi 0,%0,0\n" \ - "isync\n" \ - "b 3f\n" \ - "2: li %0,-1\n" \ - "3:\n" \ - ".section __ex_table,\"a\"\n" \ - ".balign 4\n" \ - ".long 1b,2b\n" \ - ".previous\n" \ - : "=r" (ret) : "r" (addr), "m" (*addr)); +#define GPL_DMER_MASK_DISA 0x02000000 int ppc440spe_init_pcie(void); int ppc440spe_init_pcie_rootport(int port); |