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authorRafal Jaworowski <raj@semihalf.com>2006-08-11 12:35:52 +0200
committerRafal Jaworowski <raj@pollux.denx.de>2006-08-11 12:35:52 +0200
commit36b904a7fdc170a69eb94975b0e506dc2a73fa82 (patch)
treef457aa5402f910ecb32fc8e10228a45a025e947c /cpu/ppc4xx/440spe_pcie.c
parent692519b1edfd5803cd2a841921492889f46f0ce3 (diff)
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Fix PCI-Express on PPC440SPe rev. A.
Diffstat (limited to 'cpu/ppc4xx/440spe_pcie.c')
-rw-r--r--cpu/ppc4xx/440spe_pcie.c27
1 files changed, 13 insertions, 14 deletions
diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/440spe_pcie.c
index cbc93dd..2e920aa 100644
--- a/cpu/ppc4xx/440spe_pcie.c
+++ b/cpu/ppc4xx/440spe_pcie.c
@@ -148,30 +148,28 @@ static void ppc440spe_setup_utl(u32 port) {
*/
switch (port) {
case 0:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000d);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x60000400);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0xFFFFFC01);
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800);
- utl_base = (unsigned int *)(CFG_PCIE1_REGBASE);
break;
case 1:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000d);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x60001400);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0xFFFFFC01);
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800);
- utl_base = (unsigned int *)(CFG_PCIE3_REGBASE);
break;
case 2:
- mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000d);
- mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x60002400);
- mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0xFFFFFC01);
+ mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c);
+ mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000);
+ mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001);
mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800);
- utl_base = (unsigned int *)(CFG_PCIE5_REGBASE);
break;
}
-
+ utl_base = (unsigned int *)(CFG_PCIE_BASE + 0x1000 * port);
+
/*
* Set buffer allocations and then assert VRB and TXE.
*/
@@ -182,7 +180,7 @@ static void ppc440spe_setup_utl(u32 port) {
out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000);
out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000);
out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000);
- out_be32(utl_base + PEUTL_PCTL, 0x8080007d);
+ out_be32(utl_base + PEUTL_PCTL, 0x80800066);
}
static int check_error(void)
@@ -420,6 +418,7 @@ int ppc440spe_init_pcie_rootport(int port)
* PCIE1: 0xd_2000_0000
* PCIE2: 0xd_4000_0000
*/
+
switch (port) {
case 0:
if (ppc440spe_revB()) {