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author | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2008-06-03 20:19:08 +0200 |
commit | 10a3367955bc2033b288915f8f10d0e507fe2fa1 (patch) | |
tree | c3ac82364df83db5d5cb963c64b863b77a20445c /cpu/nios2/start.S | |
parent | 97f7d27c8ecf34879d6b747c10fa9a18c02a4cc0 (diff) | |
parent | 1f1554841a4c8e069d331176f0c3059fb2bb8280 (diff) | |
download | u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.zip u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.gz u-boot-imx-10a3367955bc2033b288915f8f10d0e507fe2fa1.tar.bz2 |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'cpu/nios2/start.S')
-rw-r--r-- | cpu/nios2/start.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/cpu/nios2/start.S b/cpu/nios2/start.S index 4c6e470..6c6f294 100644 --- a/cpu/nios2/start.S +++ b/cpu/nios2/start.S @@ -178,20 +178,20 @@ _reloc: * Instruction performance varies based on the core. For cores * with icache and static/dynamic branch prediction (II/f, II/s): * - * Normal ALU (e.g. add, cmp, etc): 1 cycle - * Branch (correctly predicted, taken): 2 cycles + * Normal ALU (e.g. add, cmp, etc): 1 cycle + * Branch (correctly predicted, taken): 2 cycles * Negative offset is predicted (II/s). * * For cores without icache and no branch prediction (II/e): * - * Normal ALU (e.g. add, cmp, etc): 6 cycles - * Branch (no prediction): 6 cycles + * Normal ALU (e.g. add, cmp, etc): 6 cycles + * Branch (no prediction): 6 cycles * * For simplicity, if an instruction cache is implemented we * assume II/f or II/s. Otherwise, we use the II/e. * */ - .globl dly_clks + .globl dly_clks dly_clks: |