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author | Dave Liu <daveliu@freescale.com> | 2008-11-21 16:31:29 +0800 |
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committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
commit | 22ff3d01348e0a2dc369b7efcbac30e4ce86d178 (patch) | |
tree | e3ed66edb226e004cc85cdc4d4a966c55ce4f141 /cpu/nios2/exceptions.S | |
parent | 80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106 (diff) | |
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fsl-ddr: clean up the ddr code for DDR3 controller
- The DDR3 controller is expanding the bits for timing config
- Add the DDR3 32-bit bus mode support
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu/nios2/exceptions.S')
0 files changed, 0 insertions, 0 deletions