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| author | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-06-06 10:48:31 -0500 |
| commit | 1a247ba7fa5fb09f56892a09a990f03ce564b3e2 (patch) | |
| tree | 9dab0ef013cc6dc7883454808ecf6ba4d7a7a94e /cpu/nios/start.S | |
| parent | 2c289e320dcfb3760e99cf1d765cb067194a1202 (diff) | |
| parent | 8155efbd7ae9c65564ca98affe94631d612ae088 (diff) | |
| download | u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.zip u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.tar.gz u-boot-imx-1a247ba7fa5fb09f56892a09a990f03ce564b3e2.tar.bz2 | |
Merge commit 'wd/master'
Diffstat (limited to 'cpu/nios/start.S')
| -rw-r--r-- | cpu/nios/start.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/nios/start.S b/cpu/nios/start.S index cb1af3c..9e73941 100644 --- a/cpu/nios/start.S +++ b/cpu/nios/start.S @@ -208,7 +208,7 @@ __start: * A control register that counts system clock cycles would be * a handy feature -- hint for Altera ;-) */ - .globl dly_clks + .globl dly_clks /* Each loop is 4 instructions as delay slot is always * executed. Each instruction is approximately 4 clocks * (according to some lame info from Altera). So ... |