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authorStefan Roese <sr@denx.de>2008-06-03 20:19:08 +0200
committerStefan Roese <sr@denx.de>2008-06-03 20:19:08 +0200
commit10a3367955bc2033b288915f8f10d0e507fe2fa1 (patch)
treec3ac82364df83db5d5cb963c64b863b77a20445c /cpu/nios/start.S
parent97f7d27c8ecf34879d6b747c10fa9a18c02a4cc0 (diff)
parent1f1554841a4c8e069d331176f0c3059fb2bb8280 (diff)
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'cpu/nios/start.S')
-rw-r--r--cpu/nios/start.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/nios/start.S b/cpu/nios/start.S
index cb1af3c..9e73941 100644
--- a/cpu/nios/start.S
+++ b/cpu/nios/start.S
@@ -208,7 +208,7 @@ __start:
* A control register that counts system clock cycles would be
* a handy feature -- hint for Altera ;-)
*/
- .globl dly_clks
+ .globl dly_clks
/* Each loop is 4 instructions as delay slot is always
* executed. Each instruction is approximately 4 clocks
* (according to some lame info from Altera). So ...