diff options
| author | Dave Liu <daveliu@freescale.com> | 2009-12-16 10:24:37 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 13:49:10 -0600 |
| commit | bdc9f7b5eab8d5edd8a8cc5d80ef080836b00e85 (patch) | |
| tree | 57b6745a30901b1f9ea7b33e52dae00cbd951136 /cpu/mpc8xxx | |
| parent | 0a71c92c7e1e565111cb34cd389a21ec500ca5c1 (diff) | |
| download | u-boot-imx-bdc9f7b5eab8d5edd8a8cc5d80ef080836b00e85.zip u-boot-imx-bdc9f7b5eab8d5edd8a8cc5d80ef080836b00e85.tar.gz u-boot-imx-bdc9f7b5eab8d5edd8a8cc5d80ef080836b00e85.tar.bz2 | |
fsl-ddr: add the override for write leveling
add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx')
| -rw-r--r-- | cpu/mpc8xxx/ddr/ctrl_regs.c | 20 | ||||
| -rw-r--r-- | cpu/mpc8xxx/ddr/options.c | 1 |
2 files changed, 15 insertions, 6 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index a92f1a3..5e37ca6 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -1002,8 +1002,8 @@ static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en) } /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */ -static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, - unsigned int wrlvl_en) +static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, + const memctl_options_t *popts) { /* * First DQS pulse rising edge after margining mode @@ -1030,8 +1030,9 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, /* tWL_DQSEN min = 25 nCK, we set it 32 */ wrlvl_dqsen = 0x5; /* - * Write leveling sample time at least need 14 clocks - * due to tWLO = 9, we set it 15 clocks + * Write leveling sample time at least need 6 clocks + * higher than tWLO to allow enough time for progagation + * delay and sampling the prime data bits. */ wrlvl_smpl = 0xf; /* @@ -1044,9 +1045,16 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, * Write leveling start time * The value use for the DQS_ADJUST for the first sample * when write leveling is enabled. - * we set it 1 clock delay */ wrlvl_start = 0x8; + /* + * Override the write leveling sample and start time + * according to specific board + */ + if (popts->wrlvl_override) { + wrlvl_smpl = popts->wrlvl_sample; + wrlvl_start = popts->wrlvl_start; + } } ddr->ddr_wrlvl_cntl = (0 @@ -1332,7 +1340,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_timing_cfg_5(ddr); set_ddr_zq_cntl(ddr, zq_en); - set_ddr_wrlvl_cntl(ddr, wrlvl_en); + set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts); set_ddr_sr_cntr(ddr, sr_it); diff --git a/cpu/mpc8xxx/ddr/options.c b/cpu/mpc8xxx/ddr/options.c index 2e030c1..3dcd33d 100644 --- a/cpu/mpc8xxx/ddr/options.c +++ b/cpu/mpc8xxx/ddr/options.c @@ -198,6 +198,7 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, * meet the tQDSS under different loading. */ popts->wrlvl_en = 1; + popts->wrlvl_override = 0; #endif /* |