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authorKumar Gala <galak@kernel.crashing.org>2009-09-10 14:54:55 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-15 21:30:08 -0500
commit6d8565a1ed5acb01bad4a4cd74a93be5f7fb7f7c (patch)
treeddea3c52064b48f26d8d20f5034112ad94e65658 /cpu/mpc8xxx/ddr
parent3e3c9c157b89eab2dc2f897899b1b95cd70c1a58 (diff)
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ppc/8xxx: Misc DDR related fixes
* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong * Fix the format string to match size in a debug print Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx/ddr')
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c10
-rw-r--r--cpu/mpc8xxx/ddr/ddr3_dimm_params.c4
2 files changed, 7 insertions, 7 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 5e63c5d..2505041 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -675,12 +675,12 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
esdmode = (0
| ((qoff & 0x1) << 12)
| ((tdqs_en & 0x1) << 11)
- | ((rtt & 0x4) << 9) /* rtt field is split */
+ | ((rtt & 0x4) << 7) /* rtt field is split */
| ((wrlvl_en & 0x1) << 7)
- | ((rtt & 0x2) << 6) /* rtt field is split */
- | ((dic & 0x2) << 5) /* DIC field is split */
+ | ((rtt & 0x2) << 5) /* rtt field is split */
+ | ((dic & 0x2) << 4) /* DIC field is split */
| ((al & 0x3) << 3)
- | ((rtt & 0x1) << 2) /* rtt field is split */
+ | ((rtt & 0x1) << 2) /* rtt field is split */
| ((dic & 0x1) << 1) /* DIC field is split */
| ((dll_en & 0x1) << 0)
);
diff --git a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
index 13d234e..d4199ba 100644
--- a/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
+++ b/cpu/mpc8xxx/ddr/ddr3_dimm_params.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* calculate the organization and timing parameter
@@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width);
- debug("DDR: DDR III rank density = 0x%08x\n", bsize);
+ debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
return bsize;
}