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author | Kumar Gala <galak@kernel.crashing.org> | 2009-06-11 23:42:35 -0500 |
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committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-12 09:15:50 -0500 |
commit | e7563aff174f77aa61dab1ef5d9b47bebaa43702 (patch) | |
tree | a3ef1e9c1745d417a06328e464446436dd46f2c7 /cpu/mpc8xxx/ddr/util.c | |
parent | d4b130dc80761b430dc5b410159cd158fca1a348 (diff) | |
download | u-boot-imx-e7563aff174f77aa61dab1ef5d9b47bebaa43702.zip u-boot-imx-e7563aff174f77aa61dab1ef5d9b47bebaa43702.tar.gz u-boot-imx-e7563aff174f77aa61dab1ef5d9b47bebaa43702.tar.bz2 |
fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT
The ddr code computes most things as 64-bit quantities and had some places
in the middle that it was using phy_addr_t and phys_size_t.
Instead we use unsigned long long through out and only at the last stage of
setting the LAWs and reporting the amount of memory to the board code do we
truncate down to what we can cover via phys_size_t.
This has the added benefit that the DDR controller itself is always setup
the same way regardless of how much memory we have. Its only the LAW
setup that limits what is visible to the system.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx/ddr/util.c')
-rw-r--r-- | cpu/mpc8xxx/ddr/util.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c index 27c135b..70dbee0 100644 --- a/cpu/mpc8xxx/ddr/util.c +++ b/cpu/mpc8xxx/ddr/util.c @@ -64,6 +64,9 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num) { + unsigned long long base = memctl_common_params->base_address; + unsigned long long size = memctl_common_params->total_mem; + /* * If no DIMMs on this controller, do not proceed any further. */ @@ -71,6 +74,13 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, return; } +#if !defined(CONFIG_PHYS_64BIT) + if (base >= CONFIG_MAX_MEM_MAPPED) + return; + if ((base + size) >= CONFIG_MAX_MEM_MAPPED) + size = CONFIG_MAX_MEM_MAPPED - base; +#endif + if (ctrl_num == 0) { /* * Set up LAW for DDR controller 1 space. @@ -78,16 +88,12 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params, unsigned int lawbar1_target_id = memctl_interleaved ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1; - if (set_ddr_laws(memctl_common_params->base_address, - memctl_common_params->total_mem, - lawbar1_target_id) < 0) { + if (set_ddr_laws(base, size, lawbar1_target_id) < 0) { printf("ERROR\n"); return ; } } else if (ctrl_num == 1) { - if (set_ddr_laws(memctl_common_params->base_address, - memctl_common_params->total_mem, - LAW_TRGT_IF_DDR_2) < 0) { + if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) { printf("ERROR\n"); return ; } |