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| author | Dave Liu <daveliu@freescale.com> | 2010-03-05 12:22:00 +0800 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-04-07 00:07:23 -0500 |
| commit | ec145e87b80f6764d17a6b0aebf521fe758c3fdc (patch) | |
| tree | 41e5ea01cfc6d023c4789bdf759f447c7cc43dad /cpu/mpc8xxx/ddr/options.c | |
| parent | ab467c512e79dbd14f02352655f054a4304c457e (diff) | |
| download | u-boot-imx-ec145e87b80f6764d17a6b0aebf521fe758c3fdc.zip u-boot-imx-ec145e87b80f6764d17a6b0aebf521fe758c3fdc.tar.gz u-boot-imx-ec145e87b80f6764d17a6b0aebf521fe758c3fdc.tar.bz2 | |
fsl-ddr: Fix the turnaround timing for TIMING_CFG_4
Read-to-read/Write-to-write turnaround for same chip select
of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and
OTF case, BL/2 cycles is enough for fixed BL8.
Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2
will improve the memory performance.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'cpu/mpc8xxx/ddr/options.c')
0 files changed, 0 insertions, 0 deletions