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authorDave Liu <daveliu@freescale.com>2009-12-16 10:24:36 -0600
committerKumar Gala <galak@kernel.crashing.org>2010-01-05 13:49:10 -0600
commit0a71c92c7e1e565111cb34cd389a21ec500ca5c1 (patch)
treeabee130bc9075de43eb494b30e102a907ffda992 /cpu/mpc8xxx/ddr/options.c
parentc4ca10f1db36c3ce649c656dec14f7aab644dd86 (diff)
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fsl-ddr: Fix power-down timing settings
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc8xxx/ddr/options.c')
0 files changed, 0 insertions, 0 deletions