85xx, 86xx: Add common board_add_ram_info()

Previously, 85xx and 86xx boards would display DRAM information on
bootup such as:

...
I2C:   ready
DRAM:
Memory controller interleaving enabled: Bank interleaving!
 2 GB
FLASH: 256 MB
...

This patch moves the printing of the DRAM controller configuration to a
common board_add_ram_info() function which prints out DDR type, width,
CAS latency, and ECC mode.  It also makes the DDR interleaving
information print out in a more sane manner:

...
I2C:   ready
DRAM:   2 GB (DDR2, 64-bit, CL=4, ECC on)
       DDR Controller Interleaving Mode: bank
FLASH: 256 MB
...

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 2 insertions, 41 deletions

diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index 6dae26b..faa1af9 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -162,28 +162,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 			j++;
 		}
 	}
-	if (j == 2) {
+	if (j == 2)
 		*memctl_interleaving = 1;
 
-		printf("\nMemory controller interleaving enabled: ");
-
-		switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
-		case FSL_DDR_CACHE_LINE_INTERLEAVING:
-			printf("Cache-line interleaving!\n");
-			break;
-		case FSL_DDR_PAGE_INTERLEAVING:
-			printf("Page interleaving!\n");
-			break;
-		case FSL_DDR_BANK_INTERLEAVING:
-			printf("Bank interleaving!\n");
-			break;
-		case FSL_DDR_SUPERBANK_INTERLEAVING:
-			printf("Super bank interleaving\n");
-		default:
-			break;
-		}
-	}
-
 	/* Check that all controllers are rank interleaving. */
 	j = 0;
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
@@ -191,29 +172,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 			j++;
 		}
 	}
-	if (j == 2) {
+	if (j == 2)
 		*rank_interleaving = 1;
 
-		printf("Bank(chip-select) interleaving enabled: ");
-
-		switch (pinfo->memctl_opts[0].ba_intlv_ctl &
-						FSL_DDR_CS0_CS1_CS2_CS3) {
-		case FSL_DDR_CS0_CS1_CS2_CS3:
-			printf("CS0+CS1+CS2+CS3\n");
-			break;
-		case FSL_DDR_CS0_CS1:
-			printf("CS0+CS1\n");
-			break;
-		case FSL_DDR_CS2_CS3:
-			printf("CS2+CS3\n");
-			break;
-		case FSL_DDR_CS0_CS1_AND_CS2_CS3:
-			printf("CS0+CS1 and CS2+CS3\n");
-		default:
-			break;
-		}
-	}
-
 	if (*memctl_interleaving) {
 		unsigned long long addr, total_mem_per_ctlr = 0;
 		/*