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author | Wolfgang Denk <wd@denx.de> | 2008-10-19 02:35:50 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-10-21 11:25:39 +0200 |
commit | 8ed44d91c8122d00368523b0b746691c895d3b3c (patch) | |
tree | 7e2ff620c5b378aa82208c3e7a99e2a56570ddb7 /cpu/mpc8xx | |
parent | 08ef89ecd174969b3544f3f0c7cd1de3c57f737b (diff) | |
download | u-boot-imx-8ed44d91c8122d00368523b0b746691c895d3b3c.zip u-boot-imx-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.gz u-boot-imx-8ed44d91c8122d00368523b0b746691c895d3b3c.tar.bz2 |
Cleanup: fix "MHz" spelling
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/mpc8xx')
-rw-r--r-- | cpu/mpc8xx/fec.c | 2 | ||||
-rw-r--r-- | cpu/mpc8xx/serial.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 141425d..89c1ff9 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -398,7 +398,7 @@ static void fec_pin_init(int fecidx) * * the MII management interface clock must be less than or equal * * to 2.5 MHz. * * This MDC frequency is equal to system clock / (2 * MII_SPEED). - * * Then MII_SPEED = system_clock / 2 * 2,5 Mhz. + * * Then MII_SPEED = system_clock / 2 * 2,5 MHz. * * All MII configuration is done via FEC1 registers: */ diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index cae90dd..bd90dcd 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -70,7 +70,7 @@ static void serial_setdivisor(volatile cpm8xx_t *cp) int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate; if(divisor/16>0x1000) { - /* bad divisor, assume 50Mhz clock and 9600 baud */ + /* bad divisor, assume 50MHz clock and 9600 baud */ divisor=(50*1000*1000 + 8*9600)/16/9600; } |