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authorwdenk <wdenk>2004-04-24 23:23:30 +0000
committerwdenk <wdenk>2004-04-24 23:23:30 +0000
commite9132ea94c0182400895423c21bb04fa81f0b3f4 (patch)
treef6b5dcb9afdc85d0ef74a4fe3cda6df0dd9c267c /cpu/mpc8xx
parent5cf91d6bdc3e60bd43f9ba1bbb97a43ee49b2b2d (diff)
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Clean up the TQM8xx_YYMHz configurations; allow to use the same
binary image for all clock frequencies. Implement run-time optimization of flash access timing based on the actual bus frequency.
Diffstat (limited to 'cpu/mpc8xx')
-rw-r--r--cpu/mpc8xx/speed.c28
1 files changed, 28 insertions, 0 deletions
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index aebfbcb..165705c 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -347,4 +347,32 @@ static long init_pll_866 (long clk)
#endif /* CONFIG_MPC866_et_al */
+#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
+/*
+ * Adjust sdram refresh rate to actual CPU clock
+ * and set timebase source according to actual CPU clock
+ */
+int adjust_sdram_tbs_8xx (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ long mamr;
+ long sccr;
+
+ mamr = immr->im_memctl.memc_mamr;
+ mamr &= ~MAMR_PTA_MSK;
+ mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
+ immr->im_memctl.memc_mamr = mamr;
+
+ if (gd->cpu_clk < 67000000) {
+ sccr = immr->im_clkrst.car_sccr;
+ sccr |= SCCR_TBS;
+ immr->im_clkrst.car_sccr = sccr;
+ }
+
+ return (0);
+}
+#endif /* CONFIG_TQM8xxL/M, !TQM866M */
+
/* ------------------------------------------------------------------------- */