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authorwdenk <wdenk>2004-01-04 16:28:35 +0000
committerwdenk <wdenk>2004-01-04 16:28:35 +0000
commit180d3f74e4738ee107e269cbb949481075dd789a (patch)
treece40863d3e1b3ff07a5027d788ff1fdb5416d0d7 /cpu/mpc8xx/interrupts.c
parentdd875c767e6fb0f4fecfb799b706d84562a7acee (diff)
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* Fix problems caused by Robert Schwebel's cramfs patch
* Patch by Scott McNutt, 02 Jan 2004: Add support for the Nios Active Serial Memory Interface (ASMI) on Cyclone devices * Patch by Andrea Marson, 16 Dec 2003: Add support for the PPChameleon ME and HI modules * Patch by Yuli Barcohen, 22 Dec 2003: Add support for Motorola DUET ADS board (MPC87x/88x)
Diffstat (limited to 'cpu/mpc8xx/interrupts.c')
-rw-r--r--cpu/mpc8xx/interrupts.c20
1 files changed, 15 insertions, 5 deletions
diff --git a/cpu/mpc8xx/interrupts.c b/cpu/mpc8xx/interrupts.c
index 558dc09..20e7012 100644
--- a/cpu/mpc8xx/interrupts.c
+++ b/cpu/mpc8xx/interrupts.c
@@ -274,11 +274,21 @@ void timer_interrupt_cpu (struct pt_regs *regs)
/* Reset Timer Expired and Timers Interrupt Status */
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
__asm__ ("nop");
-#ifdef CONFIG_MPC866_et_al
- immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
-#else
- immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
-#endif
+ /*
+ Clear TEXPS (and TMIST on older chips). SPLSS (on older
+ chips) is cleared too.
+
+ Bitwise OR is a read-modify-write operation so ALL bits
+ which are cleared by writing `1' would be cleared by
+ operations like
+
+ immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS;
+
+ The same can be achieved by simple writing of the PLPRCR
+ to itself. If a bit value should be preserved, read the
+ register, ZERO the bit and write, not OR, the result back.
+ */
+ immr->im_clkrst.car_plprcr = immr->im_clkrst.car_plprcr;
}
/************************************************************************/