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authorKumar Gala <galak@kernel.crashing.org>2008-06-11 00:51:45 -0500
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-06-11 01:52:23 -0500
commit859a86a25c569d3665ff413d1d923394b8a961f3 (patch)
tree7fc7cbcb430ab3b7817f2a7817f3bbf2ea34abe8 /cpu/mpc86xx
parentf060054dadbbe7027ca088eed806a3ef1f82fdb7 (diff)
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85xx/86xx: Move to dynamic mgmt of LAWs
With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
Diffstat (limited to 'cpu/mpc86xx')
-rw-r--r--cpu/mpc86xx/cpu_init.c3
-rw-r--r--cpu/mpc86xx/spd_sdram.c6
2 files changed, 3 insertions, 6 deletions
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 0efd855..78ba1ea 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -119,8 +119,5 @@ void cpu_init_f(void)
*/
int cpu_init_r(void)
{
-#ifdef CONFIG_FSL_LAW
- disable_law(0);
-#endif
return 0;
}
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index 5cc0c26..e26db7c 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -1183,7 +1183,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 1 space.
*/
#ifdef CONFIG_FSL_LAW
- set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
+ set_next_law(CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
#endif
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
@@ -1238,7 +1238,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 1 space.
*/
#ifdef CONFIG_FSL_LAW
- set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
+ set_next_law(CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
#endif
}
@@ -1265,7 +1265,7 @@ spd_sdram(void)
* Set up LAWBAR for DDR 2 space.
*/
#ifdef CONFIG_FSL_LAW
- set_law(8,
+ set_next_law(
(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
law_size_ddr2, LAW_TRGT_IF_DDR_2);
#endif