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authorJon Loeliger <jdl@freescale.com>2006-06-15 21:33:37 -0500
committerJon Loeliger <jdl@freescale.com>2006-06-15 21:45:26 -0500
commit0e4c2a17ca34001ed36d259f13cb88ada4611a8c (patch)
tree33818fe2a6d0f97fb160c747146d4c72d6f63ddd /cpu/mpc86xx
parent8ecc971618f56029ad99d3516f8b297a6ed58971 (diff)
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Do not enable address translation on secondary CPUs.
Do not set up BATs on secondary CPUs. Let Linux do the nasty. Signed-off-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'cpu/mpc86xx')
-rw-r--r--cpu/mpc86xx/start.S15
1 files changed, 0 insertions, 15 deletions
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S
index 07e7557..12bf75b 100644
--- a/cpu/mpc86xx/start.S
+++ b/cpu/mpc86xx/start.S
@@ -1196,13 +1196,6 @@ secondary_cpu_setup:
sync
#endif
- /* setup the bats */
- bl setup_bats
- sync
- /* enable address translation */
- bl enable_addr_trans
- sync
-
/* enable and invalidate the data cache */
bl dcache_enable
sync
@@ -1211,14 +1204,6 @@ secondary_cpu_setup:
bl icache_enable
sync
- /* Set up MSR and HID0, HID1*/
- /* Enable interrupts */
-/* mfmsr r28
- li r4,0
- ori r4,r4,MSR_EE
- or r28,r28,r4
- mtmsr r28
- */
/* TBEN in HID0 */
mfspr r4, HID0