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authorTrent Piepho <tpiepho@freescale.com>2008-12-03 15:16:34 -0800
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2008-12-19 18:20:25 -0600
commita5d212a263c58cc746481bf1fc878510533ce7d6 (patch)
treeeb08c782227ec1399e96eb6dc082db2123262e41 /cpu/mpc86xx
parent58ec4866ed916c7e422f5107bb27b0822084728e (diff)
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mpc8xxx: LCRR[CLKDIV] is sometimes five bits
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'cpu/mpc86xx')
-rw-r--r--cpu/mpc86xx/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 4cace98..0ff76e3 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -110,7 +110,7 @@ checkcpu(void)
lcrr = lbc->lcrr;
}
#endif
- clkdiv = lcrr & 0x0f;
+ clkdiv = lcrr & LCRR_CLKDIV;
if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
printf("LBC:%4lu MHz\n",
sysinfo.freqSystemBus / 1000000 / clkdiv);