Merge git://www.denx.de/git/u-boot

Conflicts:

	drivers/Makefile

3 files changed, 32 insertions, 13 deletions

diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 9456471..d83bedd 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -120,7 +120,7 @@ checkcpu(void)
 static inline void
 soft_restart(unsigned long addr)
 {
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
 
 	/*
 	 * SRR0 has system reset vector, SRR1 has default MSR value
@@ -148,7 +148,7 @@ soft_restart(unsigned long addr)
 void
 do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-#ifndef CONFIG_MPC8641HPCN
+#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD)
 
 #ifdef CFG_RESET_ADDRESS
 	ulong addr = CFG_RESET_ADDRESS;
diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c
index f37ab43..265e033 100644
--- a/cpu/mpc86xx/spd_sdram.c
+++ b/cpu/mpc86xx/spd_sdram.c
@@ -948,19 +948,25 @@ unsigned int enable_ddr(unsigned int ddr_num)
 	 * Read both dimm slots and decide whether
 	 * or not to enable this controller.
 	 */
-	memset((void *)&spd1,0,sizeof(spd1));
-	memset((void *)&spd2,0,sizeof(spd2));
+	memset((void *)&spd1, 0, sizeof(spd1));
+	memset((void *)&spd2, 0, sizeof(spd2));
 
 	if (ddr_num == 1) {
 		CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
 			     0, 1, (uchar *) &spd1, sizeof(spd1));
+#if defined(SPD_EEPROM_ADDRESS2)
 		CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
 			     0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
 	} else {
+#if defined(SPD_EEPROM_ADDRESS3)
 		CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
 			     0, 1, (uchar *) &spd1, sizeof(spd1));
+#endif
+#if defined(SPD_EEPROM_ADDRESS4)
 		CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
 			     0, 1, (uchar *) &spd2, sizeof(spd2));
+#endif
 	}
 
 	/*
@@ -1105,21 +1111,27 @@ spd_sdram(void)
 {
 	int memsize_ddr1_dimm1 = 0;
 	int memsize_ddr1_dimm2 = 0;
+	int memsize_ddr1 = 0;
+	unsigned int law_size_ddr1;
+	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+#ifdef CONFIG_DDR_INTERLEAVE
+	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
+#endif
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	int memsize_ddr2_dimm1 = 0;
 	int memsize_ddr2_dimm2 = 0;
-	int memsize_total = 0;
-	int memsize_ddr1 = 0;
 	int memsize_ddr2 = 0;
+	unsigned int law_size_ddr2;
+#endif
+
 	unsigned int ddr1_enabled = 0;
 	unsigned int ddr2_enabled = 0;
-	unsigned int law_size_ddr1;
-	unsigned int law_size_ddr2;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
+	int memsize_total = 0;
 
 #ifdef CONFIG_DDR_INTERLEAVE
 	unsigned int law_size_interleaved;
-	volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
 	volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
 
 	memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
@@ -1194,9 +1206,11 @@ spd_sdram(void)
 				      (unsigned int)memsize_total * 1024*1024);
 	memsize_total += memsize_ddr1_dimm1;
 
+#if defined(SPD_EEPROM_ADDRESS2)
 	memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
 				      1, 2,
 				      (unsigned int)memsize_total * 1024*1024);
+#endif
 	memsize_total += memsize_ddr1_dimm2;
 
 	/*
@@ -1258,10 +1272,12 @@ spd_sdram(void)
 		debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
 		debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
 	}
+
+	debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2);
+
 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
 
-	debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
-	      memsize_ddr1, memsize_ddr2);
+	debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1);
 
 	/*
 	 * If neither DDR controller is enabled return 0.
diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c
index 23161ca..4f7e8f1 100644
--- a/cpu/mpc86xx/speed.c
+++ b/cpu/mpc86xx/speed.c
@@ -31,6 +31,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* used in some defintiions of CONFIG_SYS_CLK_FREQ */
+extern unsigned long get_board_sys_clk(unsigned long dummy);
+
 void get_sys_info(sys_info_t *sysInfo)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;