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| author | Dave Liu <daveliu@freescale.com> | 2008-10-28 17:46:12 +0800 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2008-10-30 10:26:37 -0500 |
| commit | dc2adad85bf580d65916c940683f6e9671e8a5dd (patch) | |
| tree | eb131f1f9ddf588a86897f0b4c09d0041ba39bf8 /cpu/mpc86xx | |
| parent | b1d0db1805c3395149777e507b6da53410abac4e (diff) | |
| download | u-boot-imx-dc2adad85bf580d65916c940683f6e9671e8a5dd.zip u-boot-imx-dc2adad85bf580d65916c940683f6e9671e8a5dd.tar.gz u-boot-imx-dc2adad85bf580d65916c940683f6e9671e8a5dd.tar.bz2 | |
86xx: Move the clear_tlbs before MMU turn on
We must invalidate TLBs before MMU turn on, but
currently the code is not, if there are some stale
TLB entry valid in the TLBs, it will cause strange
issue.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Becky Bruce <becky.bruce@freescale.com>
Diffstat (limited to 'cpu/mpc86xx')
| -rw-r--r-- | cpu/mpc86xx/start.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 159f3e1..30e6047 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -202,8 +202,12 @@ boot_warm: mtmsr 0 #endif + /* Invalidate BATs */ bl invalidate_bats sync + /* Invalidate all of TLB before MMU turn on */ + bl clear_tlbs + sync #ifdef CONFIG_SYS_L2 /* init the L2 cache */ @@ -275,7 +279,6 @@ in_flash: /* setup the rest of the bats */ bl setup_bats - bl clear_tlbs sync #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |