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| author | Jon Loeliger <jdl@freescale.com> | 2007-11-07 14:16:49 -0600 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2007-11-07 14:16:49 -0600 |
| commit | b0a41a11845259ad88897cbcf7d0d7ceb2e70844 (patch) | |
| tree | 0e2f2244762b91e517a540b361cba7cc41c0b5a8 /cpu/mpc86xx | |
| parent | 59e7965922b683a5aca44ff294d95b206d5bc58a (diff) | |
| parent | 9f23ca334a6f5f021ef9e9d0fad9da80d63b2d56 (diff) | |
| download | u-boot-imx-b0a41a11845259ad88897cbcf7d0d7ceb2e70844.zip u-boot-imx-b0a41a11845259ad88897cbcf7d0d7ceb2e70844.tar.gz u-boot-imx-b0a41a11845259ad88897cbcf7d0d7ceb2e70844.tar.bz2 | |
Merge branch 'for-1.3.0'
Diffstat (limited to 'cpu/mpc86xx')
| -rw-r--r-- | cpu/mpc86xx/cpu.c | 4 | ||||
| -rw-r--r-- | cpu/mpc86xx/spd_sdram.c | 6 |
2 files changed, 6 insertions, 4 deletions
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index bbc0cd6..11354d3 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -131,7 +131,7 @@ checkcpu(void) static inline void soft_restart(unsigned long addr) { -#ifndef CONFIG_MPC8641HPCN +#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) /* * SRR0 has system reset vector, SRR1 has default MSR value @@ -159,7 +159,7 @@ soft_restart(unsigned long addr) void do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { -#ifndef CONFIG_MPC8641HPCN +#if !defined(CONFIG_MPC8641HPCN) && !defined(CONFIG_MPC8610HPCD) #ifdef CFG_RESET_ADDRESS ulong addr = CFG_RESET_ADDRESS; diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 059097f..d57bcdf 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1270,10 +1270,12 @@ spd_sdram(void) debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8); debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8); } + + debug("\nMemory size of DDR2 = 0x%08lx\n", memsize_ddr2); + #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */ - debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n", - memsize_ddr1, memsize_ddr2); + debug("\nMemory size of DDR1 = 0x%08lx\n", memsize_ddr1); /* * If neither DDR controller is enabled return 0. |