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| author | Stefan Roese <sr@denx.de> | 2008-08-12 20:39:27 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-08-12 20:39:27 +0200 |
| commit | 9939ffd5fbf1f5aff4d8172531d4fc33797c62c8 (patch) | |
| tree | 40e9295368c82a9c7f2b09e7b1fb76c2c44df0ce /cpu/mpc86xx/start.S | |
| parent | 1c7015100a620582224f25eb057573a0fe147648 (diff) | |
| parent | cd82919e6c8a73b363a26f34b734923844e52d1c (diff) | |
| download | u-boot-imx-9939ffd5fbf1f5aff4d8172531d4fc33797c62c8.zip u-boot-imx-9939ffd5fbf1f5aff4d8172531d4fc33797c62c8.tar.gz u-boot-imx-9939ffd5fbf1f5aff4d8172531d4fc33797c62c8.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next
Diffstat (limited to 'cpu/mpc86xx/start.S')
| -rw-r--r-- | cpu/mpc86xx/start.S | 119 |
1 files changed, 0 insertions, 119 deletions
diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index c39dc46..03f2128 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -358,125 +358,6 @@ invalidate_bats: sync blr - - /* setup_bats - set them up to some initial state */ - /* Skip any BATS setup in early_bats */ - .globl setup_bats -setup_bats: - - addis r0, r0, 0x0000 - - /* IBAT 0 */ - addis r4, r0, CFG_IBAT0L@h - ori r4, r4, CFG_IBAT0L@l - addis r3, r0, CFG_IBAT0U@h - ori r3, r3, CFG_IBAT0U@l - mtspr IBAT0L, r4 - mtspr IBAT0U, r3 - isync - - /* DBAT 0 */ - addis r4, r0, CFG_DBAT0L@h - ori r4, r4, CFG_DBAT0L@l - addis r3, r0, CFG_DBAT0U@h - ori r3, r3, CFG_DBAT0U@l - mtspr DBAT0L, r4 - mtspr DBAT0U, r3 - isync - - /* IBAT 1 */ - addis r4, r0, CFG_IBAT1L@h - ori r4, r4, CFG_IBAT1L@l - addis r3, r0, CFG_IBAT1U@h - ori r3, r3, CFG_IBAT1U@l - mtspr IBAT1L, r4 - mtspr IBAT1U, r3 - isync - - /* DBAT 1 */ - addis r4, r0, CFG_DBAT1L@h - ori r4, r4, CFG_DBAT1L@l - addis r3, r0, CFG_DBAT1U@h - ori r3, r3, CFG_DBAT1U@l - mtspr DBAT1L, r4 - mtspr DBAT1U, r3 - isync - - /* IBAT 2 */ - addis r4, r0, CFG_IBAT2L@h - ori r4, r4, CFG_IBAT2L@l - addis r3, r0, CFG_IBAT2U@h - ori r3, r3, CFG_IBAT2U@l - mtspr IBAT2L, r4 - mtspr IBAT2U, r3 - isync - - /* DBAT 2 */ - addis r4, r0, CFG_DBAT2L@h - ori r4, r4, CFG_DBAT2L@l - addis r3, r0, CFG_DBAT2U@h - ori r3, r3, CFG_DBAT2U@l - mtspr DBAT2L, r4 - mtspr DBAT2U, r3 - isync - - /* IBAT 3 */ - addis r4, r0, CFG_IBAT3L@h - ori r4, r4, CFG_IBAT3L@l - addis r3, r0, CFG_IBAT3U@h - ori r3, r3, CFG_IBAT3U@l - mtspr IBAT3L, r4 - mtspr IBAT3U, r3 - isync - - /* DBAT 3 */ - addis r4, r0, CFG_DBAT3L@h - ori r4, r4, CFG_DBAT3L@l - addis r3, r0, CFG_DBAT3U@h - ori r3, r3, CFG_DBAT3U@l - mtspr DBAT3L, r4 - mtspr DBAT3U, r3 - isync - - /* IBAT 4 */ - addis r4, r0, CFG_IBAT4L@h - ori r4, r4, CFG_IBAT4L@l - addis r3, r0, CFG_IBAT4U@h - ori r3, r3, CFG_IBAT4U@l - mtspr IBAT4L, r4 - mtspr IBAT4U, r3 - isync - - /* DBAT 4 */ - addis r4, r0, CFG_DBAT4L@h - ori r4, r4, CFG_DBAT4L@l - addis r3, r0, CFG_DBAT4U@h - ori r3, r3, CFG_DBAT4U@l - mtspr DBAT4L, r4 - mtspr DBAT4U, r3 - isync - - /* IBAT 7 */ - addis r4, r0, CFG_IBAT7L@h - ori r4, r4, CFG_IBAT7L@l - addis r3, r0, CFG_IBAT7U@h - ori r3, r3, CFG_IBAT7U@l - mtspr IBAT7L, r4 - mtspr IBAT7U, r3 - isync - - /* DBAT 7 */ - addis r4, r0, CFG_DBAT7L@h - ori r4, r4, CFG_DBAT7L@l - addis r3, r0, CFG_DBAT7U@h - ori r3, r3, CFG_DBAT7U@l - mtspr DBAT7L, r4 - mtspr DBAT7U, r3 - isync - - sync - blr - /* * early_bats: * |