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author | Becky Bruce <becky.bruce@freescale.com> | 2008-11-03 15:44:01 -0600 |
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committer | Jon Loeliger <jdl@freescale.com> | 2008-11-04 10:58:50 -0600 |
commit | 1266df887781c779deaf6d05eea2ef90a470cb34 (patch) | |
tree | e38395f12d4705cc9afc4c25030e4f837e86279a /cpu/mpc86xx/mp.c | |
parent | b5431560682d8f318fbc49db87cfe13ab41d2ee4 (diff) | |
download | u-boot-imx-1266df887781c779deaf6d05eea2ef90a470cb34.zip u-boot-imx-1266df887781c779deaf6d05eea2ef90a470cb34.tar.gz u-boot-imx-1266df887781c779deaf6d05eea2ef90a470cb34.tar.bz2 |
powerpc: change 86xx SMP boot method
We put the bootpg for the secondary cpus into memory and use
BPTR to get to it. This is a step towards converting to the
ePAPR boot methodology. Also, the code is written to
deal properly with more than 4GB of RAM.
Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Diffstat (limited to 'cpu/mpc86xx/mp.c')
-rw-r--r-- | cpu/mpc86xx/mp.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c new file mode 100644 index 0000000..5014401 --- /dev/null +++ b/cpu/mpc86xx/mp.c @@ -0,0 +1,68 @@ +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <ioports.h> +#include <lmb.h> +#include <asm/io.h> +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_NUM_CPUS > 1) +void cpu_mp_lmb_reserve(struct lmb *lmb) +{ + u32 bootpg; + + /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfff00000; + else + bootpg = gd->ram_size - (1024 * 1024); + + /* tell u-boot we stole a page */ + lmb_reserve(lmb, bootpg, 4096); +} + +/* + * Copy the code for other cpus to execute into an + * aligned location accessible via BPTR + */ +void setup_mp(void) +{ + extern ulong __secondary_start_page; + ulong fixup = (ulong)&__secondary_start_page; + u32 bootpg; + u32 bootpg_va; + + /* + * If we have 4G or more of memory, put the boot page at 4Gb-1M. + * Otherwise, put it at the very end of RAM. + */ + if (gd->ram_size > 0xfffff000) + bootpg = 0xfff00000; + else + bootpg = gd->ram_size - (1024 * 1024); + + if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) { + /* We're not covered by the DDR mapping, set up BAT */ + write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K | + BATU_VS | BATU_VP, + bootpg | BATL_PP_RW | BATL_MEMCOHERENCE); + bootpg_va = CONFIG_SYS_SCRATCH_VA; + } else { + bootpg_va = bootpg; + } + + memcpy((void *)bootpg_va, (void *)fixup, 4096); + flush_cache(bootpg_va, 4096); + + /* remove the temporary BAT mapping */ + if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) + write_bat(DBAT7, 0, 0); + + /* If the physical location of bootpg is not at fff00000, set BPTR */ + if (bootpg != 0xfff00000) + out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 | + (bootpg >> 12)); +} +#endif |