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author | Kim Phillips <kim.phillips@freescale.com> | 2007-04-23 15:58:17 -0500 |
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committer | Kim Phillips <kim.phillips@freescale.com> | 2007-04-23 15:58:17 -0500 |
commit | 396955fed24c301701c83558fc6f7eadd909397b (patch) | |
tree | e022bf6f768718ce06a29280f3dfa3a0a60f90f3 /cpu/mpc86xx/interrupts.c | |
parent | 6fbf261f8df294e589cfadebebe5468e3c0f29e9 (diff) | |
parent | 14da5f7675bbb427c469e3f45006e027b6e21db9 (diff) | |
download | u-boot-imx-396955fed24c301701c83558fc6f7eadd909397b.zip u-boot-imx-396955fed24c301701c83558fc6f7eadd909397b.tar.gz u-boot-imx-396955fed24c301701c83558fc6f7eadd909397b.tar.bz2 |
Merge git://www.denx.de/git/u-boot
Diffstat (limited to 'cpu/mpc86xx/interrupts.c')
-rw-r--r-- | cpu/mpc86xx/interrupts.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 1df6cdc..49820bb 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -80,6 +80,26 @@ int interrupt_init(void) { int ret; + /* + * The IRQ0 on Rev 2 is pulled high (low in Rev 1.x) to + * implement PEX10 errata. As INT is active high, it + * will cause core to take 0x500 interrupt. + * + * Due to the PIC's default pass through mode, as soon + * as interrupts are enabled (MSR[EE] = 1), an interrupt + * will be taken and u-boot will hang. This is due to a + * hardware change (per an errata fix) on new revisions + * of the board with Rev 2.x parts. + * + * Setting the PIC to mixed mode prevents the hang. + */ + if ((get_svr() & 0xf0) == 0x20) { + volatile immap_t *immr = (immap_t *)CFG_IMMR; + immr->im_pic.gcr = MPC86xx_PICGCR_RST; + while (immr->im_pic.gcr & MPC86xx_PICGCR_RST); + immr->im_pic.gcr = MPC86xx_PICGCR_MODE; + } + /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu(&decrementer_count); |