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authorJon Loeliger <jdl@freescale.com>2007-08-02 14:42:20 -0500
committerJon Loeliger <jdl@freescale.com>2007-08-10 11:02:32 -0500
commitcfc7a7f5bb3273c9951173c788001d45118f141f (patch)
treef321b9a57ce6d32567df53a53f9d97bbc9ee9665 /cpu/mpc86xx/cpu_init.c
parent99c2fdab91bc633e46fb41dbaa629f87ccf6e00f (diff)
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cpu/86xx fixes.
Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'cpu/mpc86xx/cpu_init.c')
-rw-r--r--cpu/mpc86xx/cpu_init.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 4673d05..c8e4666 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -104,8 +104,8 @@ void cpu_init_f(void)
/* enable the timebase bit in HID0 */
set_hid0(get_hid0() | 0x4000000);
- /* enable SYNCBE | ABE bits in HID1 */
- set_hid1(get_hid1() | 0x00000C00);
+ /* enable EMCP, SYNCBE | ABE bits in HID1 */
+ set_hid1(get_hid1() | 0x80000C00);
}
/*