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| author | Jon Loeliger <jdl@freescale.com> | 2006-06-07 08:49:46 -0500 |
|---|---|---|
| committer | Jon Loeliger <jdl@freescale.com> | 2006-06-07 08:49:46 -0500 |
| commit | a941b832411ef99351a42be23ff3319643dcc1a4 (patch) | |
| tree | 1cdaa7e1e82679a5acf20676960df2b0d91d94b2 /cpu/mpc86xx/cache.S | |
| parent | 72ed528a948b151e7be5ce03ed3d2b88a229dd0a (diff) | |
| parent | c83ae9ea6d93abbe751bf8a3396236a084e56f87 (diff) | |
| download | u-boot-imx-a941b832411ef99351a42be23ff3319643dcc1a4.zip u-boot-imx-a941b832411ef99351a42be23ff3319643dcc1a4.tar.gz u-boot-imx-a941b832411ef99351a42be23ff3319643dcc1a4.tar.bz2 | |
Merge branch 'mpc86xx'
Diffstat (limited to 'cpu/mpc86xx/cache.S')
| -rw-r--r-- | cpu/mpc86xx/cache.S | 28 |
1 files changed, 17 insertions, 11 deletions
diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index 75186b1..f316b3e 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -28,7 +28,7 @@ * Most of this code is taken from 74xx_7xx/cache.S * and then cleaned up a bit */ - + /* * Invalidate L1 instruction cache. */ @@ -316,24 +316,30 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP + * Invalidate L2 cache using L2I, assume L2 is enabled */ _GLOBAL(l2cache_invalidate) - sync - oris r3, r3, L2CR_L2I@h + mfspr r3, l2cr + rlwinm. r3, r3, 0, 0, 0 + beq 1f + + mfspr r3, l2cr + rlwinm r3, r3, 0, 1, 31 + +#ifdef CONFIG_ALTIVEC + dssall +#endif sync mtspr l2cr, r3 sync +1: mfspr r3, l2cr + oris r3, r3, L2CR_L2I@h + mtspr l2cr, r3 + invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2IP + andi. r3, r3, L2CR_L2I@h bne invl2 - /* turn off the global invalidate bit */ - mfspr r3, l2cr - rlwinm r3, r3, 0, 11, 9 - sync - mtspr l2cr, r3 - sync blr /* |