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authorStefan Roese <sr@denx.de>2008-06-03 20:19:08 +0200
committerStefan Roese <sr@denx.de>2008-06-03 20:19:08 +0200
commit10a3367955bc2033b288915f8f10d0e507fe2fa1 (patch)
treec3ac82364df83db5d5cb963c64b863b77a20445c /cpu/mpc85xx
parent97f7d27c8ecf34879d6b747c10fa9a18c02a4cc0 (diff)
parent1f1554841a4c8e069d331176f0c3059fb2bb8280 (diff)
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Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/cpu.c23
-rw-r--r--cpu/mpc85xx/qe_io.c2
-rw-r--r--cpu/mpc85xx/start.S2
3 files changed, 16 insertions, 11 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 74b210c..9873383 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -174,28 +174,33 @@ int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
{
uint pvr;
uint ver;
+ unsigned long val, msr;
+
pvr = get_pvr();
ver = PVR_VER(pvr);
+
if (ver & 1){
/* e500 v2 core has reset control register */
volatile unsigned int * rstcr;
rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
*rstcr = 0x2; /* HRESET_REQ */
- }else{
+ udelay(100);
+ }
+
/*
+ * Fallthrough if the code above failed
* Initiate hard reset in debug control register DBCR0
* Make sure MSR[DE] = 1
*/
- unsigned long val, msr;
- msr = mfmsr ();
- msr |= MSR_DE;
- mtmsr (msr);
+ msr = mfmsr ();
+ msr |= MSR_DE;
+ mtmsr (msr);
+
+ val = mfspr(DBCR0);
+ val |= 0x70000000;
+ mtspr(DBCR0,val);
- val = mfspr(DBCR0);
- val |= 0x70000000;
- mtspr(DBCR0,val);
- }
return 1;
}
diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c
index 98075bb..21ea38b 100644
--- a/cpu/mpc85xx/qe_io.c
+++ b/cpu/mpc85xx/qe_io.c
@@ -34,7 +34,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
u32 pin_2bit_assign;
u32 pin_1bit_mask;
u32 tmp_val;
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
volatile par_io_t *par_io = (volatile par_io_t *)
&(gur->qe_par_io);
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 15b804d..2b5d90e 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -89,7 +89,7 @@ _start_e500:
/* L1 */
li r0,2
mtspr L1CSR0,r0 /* invalidate d-cache */
- mtspr L1CSR1,r0 /* invalidate i-cache */
+ mtspr L1CSR1,r0 /* invalidate i-cache */
mfspr r1,DBSR
mtspr DBSR,r1 /* Clear all valid bits */