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| author | Kumar Gala <galak@kernel.crashing.org> | 2007-08-07 18:07:27 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-08-14 01:45:09 -0500 |
| commit | 3db0bef59eab1155801618cef5c481e97553b597 (patch) | |
| tree | d577ba533f281f7291aa05e7a3a2a0836c1143ce /cpu/mpc85xx | |
| parent | 39980c610c9a4c381907c9e1d1b9c0e1c0dca57a (diff) | |
| download | u-boot-imx-3db0bef59eab1155801618cef5c481e97553b597.zip u-boot-imx-3db0bef59eab1155801618cef5c481e97553b597.tar.gz u-boot-imx-3db0bef59eab1155801618cef5c481e97553b597.tar.bz2 | |
Use an absolute address when jumping out of 4k boot page
On e500 when we leave the 4k boot page we should use an absolute address since
we don't know where the board code may want us to be really running at.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/start.S | 53 |
1 files changed, 24 insertions, 29 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 9dfd38d..2c98c2a 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -260,9 +260,33 @@ _start_e500: mtspr DBCR0,r0 #endif +/* L1 DCache is used for initial RAM */ + + /* Allocate Initial RAM in data cache. + */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + li r2,512 /* 512*32=16K */ + mtctr r2 + li r0,0 +1: + dcbz r0,r3 + dcbtls 0,r0,r3 + addi r3,r3,32 + bdnz 1b + /* Jump out the last 4K page and continue to 'normal' start */ +#ifdef CFG_RAMBOOT bl 3f b _start_cont +#else + /* Calculate absolute address in FLASH and jump there */ + /*--------------------------------------------------------------*/ + lis r3,CFG_MONITOR_BASE@h + ori r3,r3,CFG_MONITOR_BASE@l + addi r3,r3,_start_cont - _start + _START_OFFSET + mtlr r3 +#endif 3: li r0,0 mtspr SRR1,r0 /* Keep things disabled for now */ @@ -271,7 +295,6 @@ _start_e500: rfi isync - .text .globl _start _start: @@ -285,34 +308,6 @@ version_string: .align 4 .globl _start_cont _start_cont: - -/* L1 DCache is used for initial RAM */ - - /* Allocate Initial RAM in data cache. - */ - lis r3,CFG_INIT_RAM_ADDR@h - ori r3,r3,CFG_INIT_RAM_ADDR@l - li r2,512 /* 512*32=16K */ - mtctr r2 - li r0,0 -1: - dcbz r0,r3 - dcbtls 0,r0,r3 - addi r3,r3,32 - bdnz 1b - -#ifndef CFG_RAMBOOT - /* Calculate absolute address in FLASH and jump there */ - /*--------------------------------------------------------------*/ - lis r3,CFG_MONITOR_BASE@h - ori r3,r3,CFG_MONITOR_BASE@l - addi r3,r3,in_flash - _start + _START_OFFSET - mtlr r3 - blr - .global in_flash -in_flash: -#endif /* CFG_RAMBOOT */ - /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/ lis r1,CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET@l |