summaryrefslogtreecommitdiff
path: root/cpu/mpc85xx
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2010-03-26 15:14:43 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-03-30 10:48:30 -0500
commit33f57bd553edf29dffef5a6c7d76e169c79a6049 (patch)
treecae931b06803cf6ff873209a52e5e7dd706beb26 /cpu/mpc85xx
parent060f28532b09dd3d2c78423bdd809ac768a27629 (diff)
downloadu-boot-imx-33f57bd553edf29dffef5a6c7d76e169c79a6049.zip
u-boot-imx-33f57bd553edf29dffef5a6c7d76e169c79a6049.tar.gz
u-boot-imx-33f57bd553edf29dffef5a6c7d76e169c79a6049.tar.bz2
85xx: Fix enabling of L1 cache parity on secondary cores
Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/release.S38
-rw-r--r--cpu/mpc85xx/start.S38
2 files changed, 63 insertions, 13 deletions
diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S
index 00c4c54..dab784e 100644
--- a/cpu/mpc85xx/release.S
+++ b/cpu/mpc85xx/release.S
@@ -70,18 +70,40 @@ __secondary_start_page:
mttbu r3
/* Enable/invalidate the I-Cache */
- mfspr r0,SPRN_L1CSR1
- ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
- mtspr SPRN_L1CSR1,r0
+ lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+ ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+ mtspr SPRN_L1CSR1,r2
+1:
+ mfspr r3,SPRN_L1CSR1
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+ ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+ mtspr SPRN_L1CSR1,r3
isync
+2:
+ mfspr r3,SPRN_L1CSR1
+ andi. r1,r3,L1CSR1_ICE@l
+ beq 2b
/* Enable/invalidate the D-Cache */
- mfspr r0,SPRN_L1CSR0
- ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
- msync
- isync
- mtspr SPRN_L1CSR0,r0
+ lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+ ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+ mtspr SPRN_L1CSR0,r2
+1:
+ mfspr r3,SPRN_L1CSR0
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+ ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+ mtspr SPRN_L1CSR0,r3
isync
+2:
+ mfspr r3,SPRN_L1CSR0
+ andi. r1,r3,L1CSR0_DCE@l
+ beq 2b
#define toreset(x) (x - __secondary_start_page + 0xfffff000)
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 386fa81..af18c1c 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -108,13 +108,41 @@ _start_e500:
mtspr L1CSR2,r2
#endif
- lis r2,L1CSR0_CPE@H /* enable parity */
- ori r2,r2,L1CSR0_DCE
- mtspr L1CSR0,r2 /* enable L1 Dcache */
+ /* Enable/invalidate the I-Cache */
+ lis r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@h
+ ori r2,r2,(L1CSR1_ICFI|L1CSR1_ICLFR)@l
+ mtspr SPRN_L1CSR1,r2
+1:
+ mfspr r3,SPRN_L1CSR1
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR1_CPE|L1CSR1_ICE)@h
+ ori r3,r3,(L1CSR1_CPE|L1CSR1_ICE)@l
+ mtspr SPRN_L1CSR1,r3
isync
- mtspr L1CSR1,r2 /* enable L1 Icache */
+2:
+ mfspr r3,SPRN_L1CSR1
+ andi. r1,r3,L1CSR1_ICE@l
+ beq 2b
+
+ /* Enable/invalidate the D-Cache */
+ lis r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@h
+ ori r2,r2,(L1CSR0_DCFI|L1CSR0_DCLFR)@l
+ mtspr SPRN_L1CSR0,r2
+1:
+ mfspr r3,SPRN_L1CSR0
+ and. r1,r3,r2
+ bne 1b
+
+ lis r3,(L1CSR0_CPE|L1CSR0_DCE)@h
+ ori r3,r3,(L1CSR0_CPE|L1CSR0_DCE)@l
+ mtspr SPRN_L1CSR0,r3
isync
- msync
+2:
+ mfspr r3,SPRN_L1CSR0
+ andi. r1,r3,L1CSR0_DCE@l
+ beq 2b
/* Setup interrupt vectors */
lis r1,TEXT_BASE@h