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authorScott Wood <scottwood@freescale.com>2009-08-20 17:45:05 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-09-15 21:30:08 -0500
commitdcc87dd58db466caa2d66755c5ec9455edf42fe8 (patch)
treea1d1174bd31fc211141eb7bc8e18354219f24686 /cpu/mpc85xx
parent1b72dbecca2d7ad7a21c92d80227daa2d8ec5a57 (diff)
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ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.
Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/start.S4
-rw-r--r--cpu/mpc85xx/tlb.c3
2 files changed, 7 insertions, 0 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index eaed0e0..7a23b4f 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -156,6 +156,10 @@ _start_e500:
mtspr MCSR,r0 /* machine check syndrome register */
mtxer r0 /* clear integer exception register */
+#ifdef CONFIG_SYS_BOOK3E_HV
+ mtspr MAS8,r0 /* make sure MAS8 is clear */
+#endif
+
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
#if defined(CONFIG_ENABLE_36BIT_PHYS)
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 0497a29..03c2449 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -51,6 +51,9 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
#ifdef CONFIG_ENABLE_36BIT_PHYS
mtspr(MAS7, _mas7);
#endif
+#ifdef CONFIG_SYS_BOOK3E_HV
+ mtspr(MAS8, 0);
+#endif
asm volatile("isync;msync;tlbwe;isync");
#ifdef CONFIG_ADDR_MAP