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authorKumar Gala <galak@kernel.crashing.org>2008-01-16 09:22:29 -0600
committerKumar Gala <galak@kernel.crashing.org>2008-01-16 23:21:56 -0600
commit54a5070115eff38e9b324b78abdfa0b4520580b9 (patch)
treea183876e1c5028eaa7e85ce57005a9c3a3fb5f9b /cpu/mpc85xx
parent4d3521cc79cabc61edf12c48c0ce318d4efb712f (diff)
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85xx: Remove old style of LAW init
All boards are now using the new fsl_law code so we can drop the old version. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/spd_sdram.c10
-rw-r--r--cpu/mpc85xx/start.S18
2 files changed, 0 insertions, 28 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index bb5dc1f..90c3d44 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1023,9 +1023,6 @@ spd_sdram(void)
static unsigned int
setup_laws_and_tlbs(unsigned int memsize)
{
-#ifndef CONFIG_FSL_LAW
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
-#endif
unsigned int tlb_size;
unsigned int law_size;
unsigned int ram_tlb_index;
@@ -1104,13 +1101,6 @@ setup_laws_and_tlbs(unsigned int memsize)
#ifdef CONFIG_FSL_LAW
set_law(1, CFG_DDR_SDRAM_BASE, law_size, LAW_TRGT_IF_DDR);
-#else
- ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
- ecm->lawar1 = (LAWAR_EN
- | LAWAR_TRGT_IF_DDR
- | (LAWAR_SIZE & law_size));
- debug("DDR: LAWBAR1=0x%08x\n", ecm->lawbar1);
- debug("DDR: LARAR1=0x%08x\n", ecm->lawar1);
#endif
/*
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 346369c..2044722 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -201,24 +201,6 @@ _start_e500:
lis r7,CFG_CCSRBAR@h
ori r7,r7,CFG_CCSRBAR@l
-#ifndef CONFIG_FSL_LAW
- bl law_entry
- mr r6,r0
- lwzu r5,0(r6) /* how many windows we actually use */
- mtctr r5
-
- li r2,0x0c28 /* the first pair is reserved for */
- li r1,0x0c30 /* boot-over-rio-or-pci */
-
-0: lwzu r4,4(r6)
- lwzu r3,4(r6)
- stwx r4,r7,r2
- stwx r3,r7,r1
- addi r2,r2,0x0020
- addi r1,r1,0x0020
- bdnz 0b
-#endif
-
/* Clear and set up some registers. */
li r0,0
mtmsr r0