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authorWolfgang Denk <wd@denx.de>2009-01-14 00:26:48 +0100
committerWolfgang Denk <wd@denx.de>2009-01-14 00:26:48 +0100
commitbae6d5e4122882fdeeefdd0358ec592c01abe138 (patch)
treed3a732698cdcb5ff38037221fba78861a18bf9fe /cpu/mpc85xx
parent3e3fffe3baf3befde287fec1fcbfe55052fb8946 (diff)
parentb5f65dfa9aa8e068e62aba4733dc4fd97b1d9bf6 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/tlb.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 5b5f791..25fa9ee 100644
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -125,6 +125,10 @@ void init_addr_map(void)
}
#endif
+#ifndef CONFIG_SYS_DDR_TLB_START
+#define CONFIG_SYS_DDR_TLB_START 8
+#endif
+
unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
{
unsigned int tlb_size;
@@ -171,7 +175,7 @@ unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
* Configure DDR TLB1 entries.
* Starting at TLB1 8, use no more than 8 TLB1 entries.
*/
- ram_tlb_index = 8;
+ ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
while (ram_tlb_address < (memsize_in_meg * 1024 * 1024)
&& ram_tlb_index < 16) {