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| author | Andy Fleming <afleming@freescale.com> | 2007-04-23 01:32:22 -0500 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-04-23 19:58:28 -0500 |
| commit | 151d5d992eab8c497b24c816c73dc1ad8bffb4eb (patch) | |
| tree | fbb405be9996dcc57e20ac58491411ea2eb666ee /cpu/mpc85xx | |
| parent | 25d83d7f4ac65727182d8ddaf7ba42fa74cf65ae (diff) | |
| download | u-boot-imx-151d5d992eab8c497b24c816c73dc1ad8bffb4eb.zip u-boot-imx-151d5d992eab8c497b24c816c73dc1ad8bffb4eb.tar.gz u-boot-imx-151d5d992eab8c497b24c816c73dc1ad8bffb4eb.tar.bz2 | |
Add cpu support for the 8544
Recognize new SVR values, and add a few register definitions
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/cpu.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 2fe4f2a..2fe6bdf 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2004 Freescale Semiconductor. + * Copyright 2004,2007 Freescale Semiconductor, Inc. * (C) Copyright 2002, 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) * @@ -70,6 +70,12 @@ int checkcpu (void) case SVR_8548_E: puts("8548_E"); break; + case SVR_8544: + puts("8544"); + break; + case SVR_8544_E: + puts("8544_E"); + break; default: puts("Unknown"); break; @@ -112,7 +118,7 @@ int checkcpu (void) #endif clkdiv = lcrr & 0x0f; if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { -#ifdef CONFIG_MPC8548 +#if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) /* * Yes, the entire PQ38 family use the same * bit-representation for twice the clock divider values. |