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| author | Wolfgang Denk <wd@denx.de> | 2008-03-02 21:46:20 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-03-02 21:46:20 +0100 |
| commit | 093e14c52280b4bcc84948bac605ee4d6e87b6e9 (patch) | |
| tree | 4dcfce22cafb51d6fc316e4fdc787001ba8f7fa6 /cpu/mpc85xx | |
| parent | 5f91db7f582ca17b1f19f10189c025696f333d2e (diff) | |
| parent | 2b22fa4baee51e6b467c44ea1be0d1ecd86e8775 (diff) | |
| download | u-boot-imx-093e14c52280b4bcc84948bac605ee4d6e87b6e9.zip u-boot-imx-093e14c52280b4bcc84948bac605ee4d6e87b6e9.tar.gz u-boot-imx-093e14c52280b4bcc84948bac605ee4d6e87b6e9.tar.bz2 | |
Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx
Diffstat (limited to 'cpu/mpc85xx')
| -rw-r--r-- | cpu/mpc85xx/interrupts.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/start.S | 18 |
2 files changed, 14 insertions, 6 deletions
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c index 18e5377..4fe1fac 100644 --- a/cpu/mpc85xx/interrupts.c +++ b/cpu/mpc85xx/interrupts.c @@ -91,7 +91,7 @@ int interrupt_init (void) set_msr (get_msr () | MSR_EE); #ifdef CONFIG_INTERRUPTS - pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */ + pic->iivpr1 = 0x810001; /* 50220 enable ecm interrupts */ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1); pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index eb24dbc..15b804d 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -992,7 +992,6 @@ trap_reloc: blr -#ifdef CFG_INIT_RAM_LOCK .globl unlock_ram_in_cache unlock_ram_in_cache: /* invalidate the INIT_RAM section */ @@ -1002,11 +1001,20 @@ unlock_ram_in_cache: andi. r4,r4,0x1ff slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT) mtctr r4 -1: icbi r0,r3 - dcbi r0,r3 +1: dcbi r0,r3 addi r3,r3,CFG_CACHELINE_SIZE bdnz 1b - sync /* Wait for all icbi to complete on bus */ + sync + + /* Invalidate the TLB entries for the cache */ + lis r3,CFG_INIT_RAM_ADDR@h + ori r3,r3,CFG_INIT_RAM_ADDR@l + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 + addi r3,r3,0x1000 + tlbivax 0,r3 isync blr -#endif |