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authorKumar Gala <galak@kernel.crashing.org>2008-08-26 15:01:29 -0500
committerWolfgang Denk <wd@denx.de>2008-08-27 02:05:58 +0200
commit58e5e9aff147e8c7e2bc1406bf9384f65f020ffa (patch)
treea246c5ded0e1cdc32687c52b15483b11a0966795 /cpu/mpc85xx
parentf784e32b4bce0013983506b11af4b85b8ca3d36e (diff)
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FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.
The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx')
-rw-r--r--cpu/mpc85xx/Makefile11
1 files changed, 10 insertions, 1 deletions
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index adbc585..d51a6dd 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -33,8 +33,17 @@ SOBJS-$(CONFIG_MP) += release.o
SOBJS = $(SOBJS-y)
COBJS-$(CONFIG_MP) += mp.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+
+ifneq ($(CONFIG_FSL_DDR3),y)
+ifneq ($(CONFIG_FSL_DDR2),y)
+ifneq ($(CONFIG_FSL_DDR1),y)
+COBJS-y += spd_sdram.o
+endif
+endif
+endif
+
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \
- pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \
+ pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \
$(COBJS-y)
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)