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authorJon Loeliger <jdl@freescale.com>2008-01-10 14:28:18 -0600
committerJon Loeliger <jdl@freescale.com>2008-01-10 14:28:18 -0600
commitbb66f5613672fc80a6b38a0e1651d893bbe590a5 (patch)
tree9a8af7224b4dc2162a5cec00cf44d5afae43622f /cpu/mpc85xx/start.S
parentb830b7f1635984ba607219fcbd78597c28eeb529 (diff)
parent422b1a01602b6e2fbf8444a1192c7ba31461fd4c (diff)
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Merge commit 'wd/master'
Diffstat (limited to 'cpu/mpc85xx/start.S')
-rw-r--r--cpu/mpc85xx/start.S9
1 files changed, 7 insertions, 2 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index b769ef8..b489d2f 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -268,7 +268,10 @@ _start_e500:
*/
lis r3,CFG_INIT_RAM_ADDR@h
ori r3,r3,CFG_INIT_RAM_ADDR@l
- li r2,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r2, L1CFG0
+ andi. r2, r2, 0x1ff
+ /* cache size * 1024 / (2 * L1 line size) */
+ slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
mtctr r2
li r0,0
1:
@@ -1061,7 +1064,9 @@ unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
- li r4,(CFG_DCACHE_SIZE / (2 * CFG_CACHELINE_SIZE))
+ mfspr r4,L1CFG0
+ andi. r4,r4,0x1ff
+ slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: icbi r0,r3
dcbi r0,r3