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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-03-19 02:53:01 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 13:49:02 -0600 |
| commit | 82fd1f8da9add2d74532cf78d224485f0042d00d (patch) | |
| tree | 40c31ab6b1538c54882294ad7f2752ca60097910 /cpu/mpc85xx/start.S | |
| parent | 6ca9da4d42aeb43df5ef29f7d0518009df583b2f (diff) | |
| download | u-boot-imx-82fd1f8da9add2d74532cf78d224485f0042d00d.zip u-boot-imx-82fd1f8da9add2d74532cf78d224485f0042d00d.tar.gz u-boot-imx-82fd1f8da9add2d74532cf78d224485f0042d00d.tar.bz2 | |
85xx: Add support for e500mc cache stashing
The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.
We use the following equation to set the various stash-ids:
32 + coreID*2 + 0(L1) or 1(L2)
The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/start.S')
| -rw-r--r-- | cpu/mpc85xx/start.S | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 6a86528..7e60e67 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2009 Freescale Semiconductor. + * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -102,6 +102,12 @@ _start_e500: * */ +#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING) + /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */ + li r2,(32 + 0) + mtspr L1CSR2,r2 +#endif + lis r2,L1CSR0_CPE@H /* enable parity */ ori r2,r2,L1CSR0_DCE mtspr L1CSR0,r2 /* enable L1 Dcache */ |