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authorJon Loeliger <jdl@freescale.com>2005-07-25 14:05:07 -0500
committerJon Loeliger <jdl@freescale.com>2005-07-25 14:05:07 -0500
commitd9b94f28a442b0013caef99de084d7b72e2d4607 (patch)
tree1b293a551e021a4a696717231ec03206d9f172de /cpu/mpc85xx/start.S
parent288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2 (diff)
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* Patch by Jon Loeliger, 2005-05-05
Implemented support for MPC8548CDS board. Added DDR II support based on SPD values for MPC85xx boards. This roll-up patch also includes bugfies for the previously published patches: DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
Diffstat (limited to 'cpu/mpc85xx/start.S')
-rw-r--r--cpu/mpc85xx/start.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 7bca008..dd81899 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -174,6 +174,9 @@ _start_e500:
mtspr BUCSR,r0 /* disable branch prediction */
mtspr MAS4,r0
mtspr MAS6,r0
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+ mtspr MAS7,r0
+#endif
isync
/* Setup interrupt vectors */
@@ -358,6 +361,9 @@ _start:
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
ori r0,r0,0x4000 /* time base is processor clock */
+#if defined(CONFIG_ENABLE_36BIT_PHYS)
+ ori r0,r0,0x0080 /* enable MAS7 updates */
+#endif
mtspr HID0,r0
#if defined(CONFIG_ADDR_STREAMING)