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| author | wdenk <wdenk> | 2004-08-01 23:02:45 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-08-01 23:02:45 +0000 |
| commit | 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a (patch) | |
| tree | 812e59d74bb6ab942f7c797b6bbcc5e7c2ad4a8f /cpu/mpc85xx/start.S | |
| parent | 281e00a3be453a169d854f824a460359d10f92bb (diff) | |
| download | u-boot-imx-9aea95307fdb0ffe0d3a98a17ac73e5040c9756a.zip u-boot-imx-9aea95307fdb0ffe0d3a98a17ac73e5040c9756a.tar.gz u-boot-imx-9aea95307fdb0ffe0d3a98a17ac73e5040c9756a.tar.bz2 | |
Patch by Jon Loeliger, 16 Jul 2004:
- support larger DDR memories up to 2G on the PC8540/8560ADS and
STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
Diffstat (limited to 'cpu/mpc85xx/start.S')
| -rw-r--r-- | cpu/mpc85xx/start.S | 36 |
1 files changed, 15 insertions, 21 deletions
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 885f1ab..9207396 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -218,7 +218,19 @@ _start_e500: mtspr MMUCSR0, r2 isync - /* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. + /* + * Invalidate all TLB0 entries. + */ + li r3,4 + li r4,0 + tlbivax r4,r3 + /* + * To avoid REV1 Errata CPU6 issues, make sure + * the instruction following tlbivax is not a store. + */ + + /* + * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e. * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB * region before we can access any CCSR registers such as L2 * registers, Local Access Registers,etc. We will also re-allocate @@ -230,7 +242,7 @@ _start_e500: */ bl tlb1_entry mr r5,r0 - li r1,0x000f /* max 16 TLB1 entries */ + li r1,0x0020 /* max 16 TLB1 plus some TLB0 entries */ mtctr r1 lwzu r4,0(r5) /* how many TLB1 entries we actually use */ @@ -273,15 +285,6 @@ _start_e500: isync #endif - /* invalidate all TLB0 entries */ - li r3,4 - li r4,0 - tlbivax r4,r3 - /* - * To avoid REV1 Errata CPU6 issues, make sure - * the instruction following tlbivax is not a store. - */ - /* set up local access windows, defined at board/<boardname>/init.S */ lis r7,CFG_CCSRBAR@h @@ -289,21 +292,12 @@ _start_e500: bl law_entry mr r6,r0 -#if defined(CONFIG_RAM_AS_FLASH) - li r1,0x0006 -#else - li r1,0x0007 /*we have 8 LAWs, but reseve one for boot-over-rio-or-pci */ -#endif + li r1,0x0007 /* 8 LAWs, but reserve one for boot-over-rio-or-pci */ mtctr r1 lwzu r5,0(r6) /* how many windows we actually use */ -#if defined(CONFIG_RAM_AS_FLASH) - li r2,0x0c48 - li r1,0x0c50 -#else li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */ li r1,0x0c30 -#endif 0: cmpwi r5,0 beq 1f |