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| author | Anton Vorontsov <avorontsov@ru.mvista.com> | 2009-10-15 17:47:06 +0400 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-10-27 09:36:48 -0500 |
| commit | 7f52ed5ef1b490da282ace3316be381a6abf96a5 (patch) | |
| tree | 775e133205d0440cb47776e4b64a0442c339b1d8 /cpu/mpc85xx/speed.c | |
| parent | 48618126f78f05042dae428811809b594f747eb9 (diff) | |
| download | u-boot-imx-7f52ed5ef1b490da282ace3316be381a6abf96a5.zip u-boot-imx-7f52ed5ef1b490da282ace3316be381a6abf96a5.tar.gz u-boot-imx-7f52ed5ef1b490da282ace3316be381a6abf96a5.tar.bz2 | |
mpc85xx: Add eSDHC support for MPC8569E-MDS boards
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2
(in 1-bit mode). When eSDHC is used, we should switch u-boot console to
UART1, and make the proper device-tree fixups.
Because of an erratum in prototype boards it is impossible to use eSDHC
without disabling UART0 (which makes it quite easy to 'brick' the board
by simply issung 'setenv hwconfig esdhc', and not able to interact with
U-Boot anylonger).
So, but default we assume that the board is a prototype, which is a most
safe assumption. There is no way to determine board revision from a
register, so we use hwconfig.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/speed.c')
| -rw-r--r-- | cpu/mpc85xx/speed.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 0244b5c..7959082 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -240,8 +240,12 @@ int get_clocks (void) gd->i2c2_clk = gd->i2c1_clk; #if defined(CONFIG_FSL_ESDHC) +#ifdef CONFIG_MPC8569 + gd->sdhc_clk = gd->bus_clk; +#else gd->sdhc_clk = gd->bus_clk / 2; #endif +#endif /* defined(CONFIG_FSL_ESDHC) */ #if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; |